CMOS Digital Gate Pre-Characterization Using Equivalent Inverters

In this paper, an alternative approach for performing the pre-characterization of CMOS digital gates is proposed. This method aims to eliminate the use of circuit simulators like HSPICE during the cell pre-characterization in order to accelerate it. This procedure is necessary for the operation of technology models such as CCS, NLDM and NLPM. This is achieved by employing an analytical inverter model along with an equivalent inverter model taking advantage of the fact that digital gates can be reduced to equivalent inverter circuits. The inverter models used in this work as well as the technology requirements are briefly described. Results validate the accuracy of the proposed procedure. Keywords—Cell characterization; Gate modeling; Equivalent inverter; timing analysis; simulation;